1. Field of the Invention
The present invention pertains to the field of computer system architecture. More particularly, this invention relates to an intelligent bus bridge for implementing intelligent input/output subsystems in computer and server systems.
2. Background
High performance computer systems commonly include intelligent input/output subsystems. Such an intelligent input/output subsystem typically includes a microprocessor that performs specialized input/output functions. For example, such an intelligent input/output subsystem may perform complex communication network interface functions or disk control functions for the computer system. In such a system, the microprocessor in the intelligent input/output subsystem performs the specialized functions required according to the type of intelligent input/output subsystem.
Typically, such an intelligent input/output subsystem includes a set of specialized input/output devices coupled for communication over a component bus. Such an intelligent input/output subsystem also usually includes a local memory. The microprocessor in such an intelligent input/output subsystem typically performs the specialized input/output functions via the component bus without interfering with operations by other processors in the computer system. Such isolation of input/output transactions on the component bus typically enables improved performance by the main processor or processors in such a computer system.
Standard component buses that couple intelligent input/output subsystems to other elements of the computer system typically impose electrical loading limitations. Such electrical loading limitations impose limits on the number of components coupled to the standard component bus. For example, one prior bus standard requires that each connector on a system component interconnect bus presents only one electrical load. Such electrical loading limitations ensure that signal quality on a fully loaded bus is sufficient for reliable operation.
Some intelligent input/output subsystems contain a large number of components that communicate via a local component bus. Such a large number of components usually exceeds the electrical loading requirements imposed on each connector of a standard component bus. As a consequence, such an intelligent input/output subsystems typically includes a bus bridge circuit that couples the local component bus to other component buses in the computer system. Such a bus bridge electrically isolates the local microprocessor, the local memory and the local components of the intelligent input/output subsystem from the other component buses. Such a bus bridge circuit enables the input/output subsystem to contain the large number of components required to implement a specialized input/output function while meeting electrical loading requirements on other component buses.
Such an intelligent input/output subsystem also typically requires a large number of integrated circuit chip packages to implement such hardware functions. For example, an intelligent input/output subsystem typically includes one component that functions as a bus bridge to isolate the local component bus from the system component bus. Such an intelligent input/output subsystem also usually includes a memory controller component for controlling the local memory. In addition, such an intelligent input/output subsystem also usually includes a local microprocessor component for performing the specialized input/output functions.
Typically, the local microprocessor component, the bus bridge component, and the memory controller component are each coupled to the local component bus as independent bus agents. As a consequence, the bus bridge, the microprocessor, and the memory controller components require the implementation of a large number of input/output data pins and control pins to function as bus agents on the local component bus. Unfortunately, such a large number of input/output pins greatly increases the cost of such an intelligent input/output subsystem.
In addition, the local microprocessor in such an intelligent input/output subsystem often requires the implementation of a bus interface or bus bridge circuit between the local component bus and the native bus of the microprocessor. Such bus interfaces usually increases the component count required to implement such a system, and thereby increases the cost of such an intelligent input/output subsystem.
Moreover, the local microprocessor must typically contend with other bus agents coupled to the local component bus for access to the local memory through the memory controller. Unfortunately, such bus contentions typically reduce the performance of the local microprocessor while performing the specialized input/output functions for the intelligent input/output subsystem.